Digitization of Analog Quantities
In order for any digital device to successfully interface with an analog signal, that signal must be digitized by means of an analog-to-digital converter or ADC. This section will not endeavor to explore the intricate details of ADC circuitry, but merely to discuss ADC performance in the context of process measurements.
Many of the concerns discussed in this section are relevant to circuits converting digital values into analog signals as well. These digital-to-analog converters, or DACs, are generally used to produce the analog drive signals required of final control elements (e.g. the output of a digital PID controller driving a 4-20 mA analog signal to a control valve positioner).
In its simplest form, an ADC is an electronic circuit receiving an analog voltage signal input and generating a multi-bit binary (digital) output. Perhaps the most obvious measure of ADC performance, then, is how many bits of output are provided:
The ADC shown in the above illustration is a 12-bit unit. This means its digital output ranges from 000000000000 to 111111111111 (000 hexadecimal to FFF hexadecimal, or 0 decimal to 4095 decimal). Although the ADC shown outputs its digital data in parallel form (with separate terminals for the 12 individual bits), many modern ADC chips are designed for serial data output, where a single terminal generates a sequential series of bits timed to the pulse of a clock signal.
Supposing this 12-bit ADC has an analog input voltage range of 0 to 10 volts, how do we relate any given digital number value to a voltage value, or visa-versa? The key here is to understand that the 12-bit resolution of this ADC means it has 212, or 4096, discrete output states. The 10 volt DC input range is therefore divided up into 212 − 1, or 4095, discrete increments:
n = Number of binary bits in the output “word”
For our hypothetical 0-10 VDC, 12-bit converter, the analog resolution is 2.442 millivolts. Thus, for any analog signal between 0 mV and 2.442 mV, the ADC’s output should be zero (binary 000000000000); for any analog signal between 2.442 mV and 4.884 mV, the ADC’s output should be one (binary 000000000001); and so on.
The digital output value from an industrial ADC is commonly referred to as a count. The word “count” is used in this context as a unit of measurement. For instance, if we subjected our 12-bit ADC to a full-scale input signal of 10 VDC, we would expect to see a full-scale digital output (binary 111111111111) of 4095 “counts.” Since most ADC circuits are designed to be linear, the mathematical relationship between input voltage and digital output “counts” is a simple proportionality:
We may use this formula to generate a partial table of input and output values for our 0-10 VDC, 12-bit ADC:
|Vin||Vin Counts (decimal)||Counts (hex)|
In order to calculate a digital count value from a given input voltage, simply divide that voltage value by the full-scale voltage, then multiply by the full-scale count value and round down to the nearest whole number. For any given voltage value input to the ADC, there is exactly one corresponding output “count” value. The converse cannot be said, however: for any given output “count” value, there is actually a small range of possible input voltages (that range being the analog resolution of the ADC, in this case 2.442 mV).
To illustrate, let us take one of the table entries as an example: an analog input of 6.11 volts should yield a digital output of (precisely) 2502 counts. However, a digital output of 2502 counts could represent any analog input voltage ranging between 6.10989 volts and 6.11233 volts. This uncertainty is inherent to the process of “digitizing” an analog signal: by using a discrete quantity to represent something infinitely variable, some detail is inevitably lost. This uncertainty is referred to as quantization error: the (potential) error resulting from “quantizing” (digitizing) an inherently analog quantity into a discrete representation.
Quantization error may be reduced (but never eliminated) by using an ADC with greater resolution. A 14-bit ADC operating over the same 0-10 VDC analog input range would have approximately one-quarter the uncertainty of the 12-bit ADC (0.610 mV instead of 2.442 mV). A 16-bit ADC’s uncertainty would only be (approximately) one-sixteenth that of the 12-bit ADC. The number of bits chosen for any particular ADC application is therefore a function of how precise the digitization must be.
Often you will encounter digital instruments where the digital “count” scale maps to a live-zero analog range. For example, the Siemens model 353 process controller represents process variable, setpoint, and output (“valve”) percentages on a scale of -3.3% to 103.3% with a 12-bit ADC count. For this controller, a digital count of 0 represents an analog signal of -3.3%, and a digital count value of FFF hexadecimal represents 103.3%. We may show the relationship between these two scales in graphical form, like a number line:
Converting a digital count value to its respective analog percentage (or visa-versa) follows the same procedure used to convert values between any two representative scales where one of the scales has a “live zero:” take the given value and convert to a percentage of span (subtracting any live zero before dividing by the span), then calculate the other value based on that percentage of span (adding any live zero after multiplying by the span).
For example, to determine what the representative digital count value would be for an analog signal having a percentage value of 26.7% on this scale, all we need to do is determine how much of the maximum digital count value this is:
Here, the analog signal value of 26.7% is 30% away from the scale’s starting point of -3.3%. Compared to the scale’s span of 106.6%, this is a value of:
Since we know a 12-bit binary count goes from 0 to 4095, and our current 26.7% analog signal value places us at 28.14% of the 4095 full-scale count, the count value for this analog signal should be 1152, or 480 hexadecimal (480h).
Similarly, if we knew the range of this 12-bit ADC in actual process engineering units, we could translate between ADC counts and the process value by the same method. Suppose we used one of these same controllers to display the temperature of a furnace, where the lower- and upper-range values were 900 deg F and 1850 deg F, respectively. We could relate the ADC count to the temperature scale using the same “number line” format as the previous example:
Suppose the ADC count for a certain furnace temperature was A59 hexadecimal (A59h), equal to 2649 in decimal form:
To convert this count value into a temperature, first we determine its percentage of span:
Next, we calculate the how much of the temperature scale’s span this equates to:
Thus, this temperature is 614.5 degrees hotter than the bottom of the scale (at 900 deg F).
Adding the live zero value of 900 degrees F, we arrive at a furnace temperature of 1514.5 degrees F.
The next major performance metric for analog signal digitization is how often the analog signal gets converted into digital form. Each time an ADC circuit “samples” its analog input signal, the resulting digital number is fixed until the next sample. This is analogous to monitoring a continuously moving process by taking a series of still-photographs. Any changes happening to the analog signal between sampling events are not detected by the converter, and therefore are not represented in the digital data coming from the converter.
It stands to reason, then, that the sampling rate of any ADC must be at least as often as significant changes are expected to take place in the analog measurement. According to the Nyquist Sampling Theorem, the absolute minimum sample rate necessary to capture an analog waveform is twice the waveform’s fundamental frequency. More realistic is to have the ADC sample the waveform ten times or more per cycle.
In general electronics work, for example with the design of electronic test equipment such as digital multimeters (DMMs) and digital storage oscilloscopes (DSOs), sampling rates must be rather fast. Modern digital oscilloscopes may have sampling rates in the billions of samples per second, to allow for the successful digitization of radio-frequency analog signals.
Industrial process measurements are far more forgiving than measurements commonly performed on an electronic technician’s workbench, thankfully. The temperature of a large furnace may be adequately sampled at a rate of only once per minute, if need be. Even “fast” feedback processes such as liquid flow and pressure control may be controlled with reasonable stability by digital systems sampling just a few times per second.
A sampling rate that is too slow (infrequent) may detrimentally affect an instrumentation in more than one way. First, the time between samples is dead time to the system: time during which the digital system will be completely unresponsive to any changes in process measurement. Excessive dead time in an alarm system means an unnecessary time delay between the alarm event and the alarm signal. Excessive dead time in a feedback control loop leads to oscillation and instability. Another detrimental effect of low sampling rate is something called aliasing: a condition where the digital system “thinks” the frequency of an analog signal is far lower than it actually is.
A dramatic example of aliasing is shown in the following illustration, where a sinusoidal signal (colored blue) is sampled at intervals slightly slower than once per cycle (samples marked by red dots). The result (the red, dashed curve) is what appears to be a much lower-frequency signal as seen by the digital system, which only “sees” the values represented by the red dots:
The troubling nature of aliasing is that it causes the ADC to report a completely incorrect, yet completely plausible signal. One simple way to avoid aliasing in an ADC circuit is to place an analog low-pass filter circuit before the ADC’s input, preventing any analog signals with frequencies beyond the Nyquist limit to pass through to the ADC. Such a “front-end” circuit is called an anti-aliasing filter :
Aliasing may still occur within digital systems, though, if one portion of a system “samples” the digital output of another portion at a substantially lower frequency. An example of this might be the rate at which a digital control system (such as a DCS) polls a process variable value collected by a digital sensor network (such as a network of radio-linked process transmitters, or digital fieldbus transmitters). If the DCS polling rate is sufficiently slow compared to the frequency of the signal reported by the digital transmitters, aliasing may result. The best guard against such potential troubles is to synchronize the sampling rates throughout the system.
- Digital Data Communication Theory
- Introduction - Digital Data Acquisition and Networks
- EIA/TIA-232, 422, and 485 Networks
- Ethernet Networks
- Internet Protocol (IP)
- Transmission Control Protocol (TCP) and User Datagram Protocol (UDP)
- The HART Digital/Analog Hybrid Standard
- Damping Adjustments
- INDUSTRIAL CONTROL HANDBOOK - 1.1 QUALITY OF SENSORS